1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and more particularly relates to a word line reset circuit for a semiconductor memory circuit and a word line reset method.
2. Description of the Related Art
FIG. 3 is a partial circuit diagram of a semiconductor memory circuit. As shown in FIG. 3, a large number of memory cells 10 (only some of which are shown in FIG. 3, with the remainder being omitted) are arrayed horizontally and vertically, so as to comprise a memory cell array 12. The memory cell array 12 is arranged in a grid, with word lines 14 and bit lines 16 at right-angles with respect to each other. Each memory cell 10 is then connected to one word line 14 and one bit line 16.
In the case of the one transistor, one capacitor-type DRAM memory cell 10 shown in FIG. 3, a transistor gate is connected to a word line 14 and another terminal of the transistor is connected to a bit line 16. Word line driver circuits (hereinafter referred to as word line reset circuits) 18 are connected to the word lines 14. A word line reset circuit 18 selects one of the word lines 14 and applies an H-level potential to the selected word line 14. This turns the transistor of the memory cell 10 connected to the selected word line 14 on and the charge of a capacitor is transmitted to the bit line 16. On the other hand, L-level potentials are applied to word lines that are not selected. As a result, transistors of memory cells 10 connected to unselected word lines 14 are off and capacitor charge is held without being transmitted to the bit lines 16.
When another word line 14 is then subsequently selected, it is necessary to make the H-level of the previously selected word line an L-level. This operation is referred to as a "reset", and in related memory circuits this is achieved by connecting previously selected word lines 14 to an earth supply line at an L-level.
If a connected word line 14 is put to ground, a transistor of a memory cell 10 is turned off. However, the potential of the earth line temporarily rises because the charge on the selected word line flows to the earth supply line due to this reset operation. This situation is referred to as the occurrence of noise, and in this case the potential of non-selected word lines temporarily rises above ground. This results in the problem of charge leaking to bit lines from capacitors of memory cells 10 connected to unselected word lines. Ways of making the potential of unselected word lines lower than ground are disclosed in Japanese Patent Laid-open Publication Nos. Hei. 9-134591 and 11-250655, and U.S. Pat. Nos. 5,617,367 and 5,410,508.
However, even if the level of unselected word lines is set to a lower level than ground, noise occurs when the word lines are reset and charge accumulated at the capacitors of the memory cells leaks.